Patent · US Active

Tile subsystem and method for automated data flow and data processing within an integrated circuit architecture

US12014214B2 · kind B2 · utility

0Cited by
1References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 15, 2021
Grant dateJun 18, 2024
Priority date
Expiry dateOct 29, 2042

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06N3/048
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.