Word line driver array and memory
US12014801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2022 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Dec 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present application relate to the field of semiconductors, and provide a word line driver array and a memory. The word line driver array at least includes: a first transistor, a third transistor, a fourth transistor and a second transistor arranged sequentially, as well as a fourth word line, a first word line, a second word line and a third word line parallel to each other, wherein the fourth word line is connected to a drain of the fourth transistor, the first word line is connected to a drain of the first transistor, the second word line is connected to a drain of the second transistor, and the third word line is connected to a drain of the third transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.