Systems and methods for wafer-level photonic testing
US12014962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2023 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Jul 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/503
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.