Electro-migration reduction
US12014987B2 · kind B2 · utility
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13References
20Claims
0Family size
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Key dates
| Filing date | Jul 20, 2022 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Jul 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.