Array substrate and method for manufacturing the same, display panel and display device
US12015033B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 30, 2020 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Jan 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes a base, a first conductive layer disposed at a side of the base, an insulating layer disposed at a side of the first conductive layer away from the base, and a second conductive layer disposed at a side of the insulating layer away from the first conductive layer. The insulating layer is provided with a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor. The second conductive layer includes a first conductive connection portion, and the first conductive connection portion connects the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.