Field effect transistor with controllable resistance
US12015056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2023 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
Abstract
A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.