Manufacturing method of semiconductor power device
US12015078B2 · kind B2 · utility
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2References
9Claims
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Key dates
| Filing date | Nov 12, 2020 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Nov 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor power device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer, a second insulating layer, and a third insulating layer as a mask to form a second groove in the n-type substrate. A fourth insulating layer and a gate are formed in the second groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.