Quantum chip test structure and fabrication method therefor, and test method and fabrication method for quantum chip
US12016253B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2023 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | May 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are a quantum chip test structure and a fabrication method therefor, and a test method and a fabrication method for a quantum chip. The quantum chip test structure includes: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, where a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, where a deposition window is formed in the second isolation layer; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, and the electrical connection layer is configured to implement electrical contact with a test device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.