Processing system, related integrated circuit, device and method
US12019118B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 20, 2023 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Mar 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0754
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.