Array substrate and display panel
US12019342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Jul 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a display panel are provided. The array substrate includes a plurality of data lines and scan lines intersecting to form a plurality of subpixel units. Each of the subpixel units includes a substrate, a common electrode layer, and an active layer. The active layer includes at least a first active layer and at least a second active layer. The first active layer is located in a thin-film transistor included in the array substrate, and at least one of the second active layers is not located at a position where the common electrode layer and the data line overlap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.