Core off sleep mode with low exit latency
US12019498B2 · kind B2 · utility
0Cited by
7References
35Claims
0Family size
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Key dates
| Filing date | Oct 30, 2018 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Jan 6, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.