Integrated circuit including standard cell and method of manufacturing the integrated circuit
US12019965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Jul 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.