Instruction execution method and instruction execution device
US12020034B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Nov 4, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Nov 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30189
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction execution method for a microprocessor is provided. The microprocessor includes a model specific register (MSR). And, the instruction execution method includes the following steps. A target instruction is received using an instruction cache. The target instruction is decoded using an instruction translator to determine whether the target instruction is a specific instruction is a specific instruction. When the target instruction is the specific instruction, a model specific register index of the target instruction is obtained to directly read or write the model specific register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.