Compute kernel parsing with limits in one or more dimensions with iterating through workgroups in the one or more dimensions for execution
US12020075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2020 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Apr 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to dispatching compute work from a compute stream. In some embodiments, a graphics processor executes instructions of compute kernels. Workload parser circuitry may determine, for distribution to the graphics processor circuitry, a set of workgroups from a compute kernel that includes workgroups organized in multiple dimensions, including a first number of workgroups in a first dimension and a second number of workgroups in a second dimension. This may include determining multiple sub-kernels for the compute kernel, wherein a first sub-kernel includes, in the first dimension, a limited number of workgroups that is smaller than the first number of workgroups. The parser circuitry may iterate through workgroups in both the first and second dimensions to generate the set of workgroups, proceeding through the first sub-kernel before iterating through any of the other sub-kernels. Disclosed techniques may provide desirable shapes for batches of workgroups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.