Neural network processor
US12020151B2 · kind B2 · utility
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Key dates
| Filing date | May 13, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | May 30, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each processor of the SIMD array performs the computations for a respective neuron of a neural network. As part of this computation, each processor of the SIMD array multiplies an input to a weight and accumulates the result for its assigned neuron each (MAC) instruction cycle. A table in a first memory is used to store which input is fed to each processor of the SIMD array. A crossbar is used to route a specific input to each processor each MAC cycle. A second memory is used to provide the appropriate weight to each processor that corresponds the input being routed to that processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.