Vertical channel thin film transistor and method for manufacturing the same
US12021151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Oct 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6755
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.