Equalization in high-speed data channel having sparse impulse response
US12021670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2023 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Jun 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03579
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A physical layer transceiver, for connecting a host device to a wireline channel medium that is divided into a total number of link segments, includes a host interface for coupling to a host device, a line interface for coupling to the wireline channel medium, and feed-forward equalization (FFE) circuitry operatively coupled to the line interface to add back, into a signal, components that were scattered in time. Respective individual filter segments are selectably configurable, by adjustment of respective delay lines, to correspond to respective individual link segments. The FFE circuitry also includes control circuitry configured to detect a signal energy peak in at least one particular link segment and, upon detection of the signal energy peak in the particular link segment, configure a respective one of the respective individual filter segments, by adjustment of a respective delay line, to correspond to the respective particular link segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.