Semiconductor memory device
US12022657B2 · kind B2 · utility
0Cited by
7References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 1, 2023 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Mar 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.