Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit
US12026041B2 · kind B2 · utility
0Cited by
2References
10Claims
0Family size
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Inventor
Key dates
| Filing date | Sep 20, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Oct 6, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.