DDR DIMM, memory system and operation method thereof
US12026050B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Nov 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double data rate dual-in-line memory module (DDR DIMM), a memory system and an operation method thereof using a data buffer for error correction are disclosed. In an example, the DDR DIMM includes a first channel including a first group of DRAM chips and a first data buffer corresponding to the first group of DRAM chips; wherein: the first data buffer is configured to obtain all write data signals input to the first channel, encode write data of all the write data signals to generate a first ECC, and send the first ECC and the write data to the first group of DRAM chips in a write operation. The disclosure can realize excellent error detection and error correction within the memory module and can greatly reduce bit error rate of the entire memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.