Method and system of low pin count (LPC) bus serial interrupt
US12026111B2 · kind B2 · utility
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9References
20Claims
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Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Feb 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low pin count (LPC) bus serial interrupt system includes: an interrupt direction signal generator configured to determine a current interrupt direction signal according to whether a host currently sends a first interrupt signal to an external device; and a level-shifter configured to convert a voltage level of a signal exchanged between the host and the external device according to the current interrupt direction signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.