Compensating DC loss in USB 2.0 high speed applications
US12026115B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 19, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Oct 19, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.