Patent · US Active

Network and edge acceleration tile (NEXT) architecture

US12026116B2 · kind B2 · utility

2Cited by

3References

26Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Patrick G. Kutch · Tigard, US
Andrey Chilikin · Limerick, IE
Niall D. McDonnell · Limerick, IE
Brian Andrew Keating · Shannon, IE
Naveen Lakkakula · Chandler, US
Ilango S. Ganga · Cupertino, US
Venkidesh Krishna Iyer · Chandler, US
Patrick Fleming · Pine Island, US
Lokpraveen Mosur · Worcester, US

Key dates

Filing date	Dec 26, 2020
Grant date	Jul 2, 2024
Priority date	—
Expiry date	Nov 3, 2041

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.