Configurable flash memory physical interface in a host device
US12026369B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory physical interface in a host device may be configured based on a selection signal indicating whether a flash memory system is a first type or a second type. Based on the selection signal, either a first differential memory data signal input of driver circuitry or a second differential memory data signal input of the driver circuitry may be coupled to a differential data input of the flash memory system. Based on the selection signal, a differential data output of the flash memory system may be coupled to either a first differential memory data signal output of receiver circuitry or a second differential memory data signal output of the receiver circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.