Using cycle counts to serve compute elements executing statically scheduled instructions for a machine learning accelerator
US12026510B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2023 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Feb 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A machine learning accelerator (MLA) implemented on a semiconductor die includes a computing mesh of interconnected compute elements that includes storage elements (SEs) and processing elements (PEs). The compute elements execute a program of instructions to implement a machine learning network according to a static schedule for execution of the instructions. A compiler determines allowable time windows for the transfer of instructions and/or data from off-chip memory to the compute elements in order to fulfill the static schedule. If instructions/data are available before the time window opens, they are held until the window opens. If the window is about to close and the transfer of instructions/data is not yet complete, the execution of statically scheduled instructions is suspended to allow the transfer to complete within the window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.