Processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process
US12026628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Nov 10, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A broadcast subsystem of a processor system includes: a set of broadcast buses, each broadcast bus in the set of broadcast buses electrically coupled to a subset of primary memory units in the set of primary memory units; a primary memory unit queue: configured to store a first set of data transfer requests associated with the set of primary memory units; electrically coupled to the data buffer a broadcast scheduler: electrically coupled to the primary memory unit queue; electrically coupled to the set of broadcast buses; and configured to transfer source data from the data buffer to a target subset of primary memory units in the set of primary memory units via the set of broadcast buses based on the set of data transfer requests stored in the primary memory unit queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.