Memory device and method for performing consecutive memory accesses

US12027200B2 · kind B2 · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Andre Guntoro · Weil der Stadt, DE
• Chirag Sudarshan · Kaiserslautern, DE
• Christian Weis · Scheidegg, DE
• Leonardo Luiz Ecco · Stuttgart, DE
• Taha Soliman · Renningen, DE
• Norbert Wehn · Queidersbach, DE

Key dates

• Filing date: May 17, 2022
• Grant date: Jul 2, 2024
• Expiry date: Sep 21, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/22
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory device comprising a plurality of memory cells situated in a first cell field, multiple first bit lines, each respectively connected to multiple memory cells of the first cell field to enable access to the memory cells via the bit line, and multiple sense amplifier pairs which respectively comprise a first and a second sense amplifier. Each first bit line is assigned to a sense amplifier pair, each first bit line being connected to a respective first semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the first sense amplifier of the sense amplifier pair, to which the bit line is assigned. Each first bit line is connected to a respective second semiconductor switch element, through which the bit line is electroconductively connectible to and insulatable from the second sense amplifier of the sense amplifier pair, to which the bit line is assigned.