Column select signal cell circuit, bit line sense circuit and memory
US12027201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Jun 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column select signal cell circuit, a bit line sense circuit and a memory are disclosed. The column select signal cell circuit includes four column select cells, each of which includes 4*N input and output ports, 4*N bit line connection ports and one control port. The control ports of a first column select cell and a fourth column select cell are connected to a first column select signal, and the control ports of a second column select cell and a third column select cell are connected to a second column select signal. The bit line connection ports of the first column select cell and the third column select cell are connected to 8*N bit lines of a first storage unit group, the bit line connection ports of the second column select cell and the fourth column select cell are connected to 8*N bit lines of a second storage unit group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.