Voltage control in semiconductor memory device
US12027208B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Aug 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a decoder circuit, a voltage supply circuit, and a control circuit. The voltage supply circuit is configured to generate a first voltage supplied to the decoder circuit, a second voltage supplied to a select gate line, and a third voltage supplied to a word line. The control circuit, during a read operation with respect to a memory cell transistor, starts a first control operation on the voltage supply circuit to boost the first voltage to a first target voltage, during the first control operation, starts a second control operation to boost the second voltage, and during the second control operation, starts a third control operation to boost the third voltage. During the first control operation, the first voltage is increased to and maintained at an intermediate voltage lower than the first target voltage for a certain period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.