Word line driver circuit and memory
US12027232B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Dec 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A word line driver circuit may at least include multiple word line drivers, each of which including a PMOS transistor and at least one NMOS transistor. The multiple word line drivers include multiple PMOS transistors and multiple NMOS transistors. The multiple PMOS transistors are arranged side by side, and in an arrangement direction of the multiple PMOS transistors, a part of the multiple NMOS transistors are located on a side of the multiple PMOS transistors, and another part of the NMOS transistors are located on another side of the multiple PMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.