Conductive route patterning for electronic substrates

US12027466B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jeremy Ecton · Gilbert, US
• Aleksandar Aleksov · Chandler, US
• Brandon C. Marin · Chandler, US
• Yonggang Li · Chandler, US
• Leonel Arana · Phoenix, US
• Suddhasattwa Nad · Chandler, US
• Haobo Chen · Chandler, US
• Tarek A. Ibrahim · Mesa, US

Key dates

• Filing date: Sep 21, 2020
• Grant date: Jul 2, 2024
• Expiry date: Aug 16, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K2201/10734
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.