Methods of forming stacked integrated circuits using selective thermal atomic layer deposition on conductive contacts and structures formed using the same

US12027488B2 · kind B2 · utility

Assignees

• The Regents of the University of California · US
• Wayne State University · US
• Georgia Tech Research Corporation · US

Inventors

• Mike Breeden · Village of La Jolla, US
• Victor Wang · Orange, US
• Andrew C. Kummel · San Diego, US
• Ming Li · Ningbo City, CN
• Muhannad Bakir · Atlanta, US
• Jonathan Hollin · Albany, US
• Nyi Myat Khine Linn · Detroit, US
• Charles H. Winter · Bloomfield, US

Key dates

• Filing date: Sep 9, 2021
• Grant date: Jul 2, 2024
• Expiry date: Sep 15, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/01074
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.