Receivers for high density and low latency chip-to-chip links
US12028057B2 · kind B2 · utility
0Cited by
10References
35Claims
0Family size
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Key dates
| Filing date | Sep 23, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Sep 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes a receiver. The receiver includes an input stage having an input and an output, and a first resistor coupled between the output of the input stage and the input of the input stage. The receiver also includes an output stage having an input and an output, wherein the input of the output stage is coupled to the output of the input stage, and a feedback path coupled between the output of the output stage and the input of the input stage, the feedback path including a second resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.