Self calibrating digital-to-analog converter
US12028086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Jan 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fL and fH once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.