Software-defined guaranteed-latency networking
US12028265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | May 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/629
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Various embodiments relate to a path computation element (PCE) configured to control a network having ingress edge nodes, interior nodes, and egress edge nodes, including: a network interface configured to communicate with the network; a memory; and a processor coupled to the memory and the network interface, wherein the processor is further configured to: receive a request for a first continuous guaranteed latency (CGL) flow to be carried by the network; make routing and admission control decisions for the requested first CGL flow without provisioning of the first CGL flow and the configuration of schedulers in the interior nodes of the network; and provide flow shaping parameters to a flow shaper at an ingress edge node of the first CGL flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.