Resistive memory device
US12029048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2021 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Feb 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/882
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.