Array substrate and display panel
US12032259B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 19, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Jul 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/134309
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a display panel are provided. Pixel units of the array substrate include a thin film transistor region, pixel electrode regions, thin film transistors disposed in the thin film transistor region, and pixel electrodes disposed in the pixel electrode regions. The pixel electrode is electrically connected to the thin film transistor. Meanwhile, a shielding member is further disposed in the thin film transistor region, and an interval between the shielding member and the pixel electrode in an extending direction of data lines is a first threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.