Computer-implemented method for defect analysis, computer-implemented method of evaluating likelihood of defect occurrence, apparatus for defect analysis, computer-program product, and intelligent defect analysis system
US12032364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2020 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Mar 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A computer-implemented method for defect analysis is provided. The computer-implemented method includes calculating a plurality of weight-of-evidence (WOE) scores respectively for a plurality of device operations with respect to detects occurred during a fabrication period, a higher WOE score indicating a higher correlation between a defect and a device operation; and ranking the plurality of WOE scores to obtain a list of selected device operations highly correlated with the defects occurred during the fabrication period, device operations in the list of selected device operations having a WOE score greater than a first threshold score. A respective one of the plurality of device operations is a respective device defined by a respective operation site at which the respective device perform a respective operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.