Systems and methods for an ECC architecture with memory mapping
US12032441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2023 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Jun 30, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.