Managing peripheral component interconnect express slots of an information handling system
US12032507B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2023 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Feb 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing PCIe slots, including identifying a table, stored at a database, indicating, for each PCIe card, a number of PCIe slots to be designated as inaccessible to other PCIe cards; detecting coupling of a particular PCIe card to a particular PCIe slot; accessing, in response to detecting the coupling of the particular PCIe card to the particular PCIe slot, the table; determining, based on the accessing, that the table includes data indicating the particular PCIe card; identifying, based on determining that the table includes data indicating the particular PCIe card, the number of PCIe slots adjacent to the particular slot to be designated as inaccessible to other PCIe cards; adjusting, based on the number of PCIe slots adjacent to the particular slot to be designated as inaccessible to other PCIe cards, a power state of one or more PCIe slots adjacent to the particular PCIe slot to an off-power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.