Memory coupled compiling method and system of reconfigurable chip
US12032841B2 · kind B2 · utility
2Cited by
4References
18Claims
0Family size
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Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Oct 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a memory coupled compiling method and system of a reconfigurable chip. The memory coupled compiling method includes: acquiring a cycle number of a data flow graph (DFG); acquiring a linear transformation vector of the cycle number through a mapping time difference; determining whether a linear array of the linear transformation vector is acquired by a heuristic algorithm; acquiring a memory mapping result through a current DFG or acquiring a cycle number of the current DFG until the linear array is acquired, depending on the determination result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.