Methods and circuits for power management of a memory module
US12033683B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 20, 2022 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Oct 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.