Clock circuit and memory
US12033684B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Jul 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock circuit and a memory are provided. The clock circuit includes a data strobe clock circuit and a system clock circuit. The data strobe clock circuit is configured to receive and transmit a data strobe clock signal, the data strobe clock signal is used for controlling at least one of receiving or sending of a data signal. The system clock circuit is configured to receive and transmit a system clock signal, the system clock signal is used for controlling receiving of a command signal. The system clock circuit includes at least two first signal transmission paths, and is configured to transmit the system clock signal via different first signal transmission paths in the at least two first signal transmission paths based on at least one of: different receiving rates, or different sending rates of the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.