Memory device adjusting duty cycle and memory system having the same
US12033686B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 9, 2023 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | May 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.