Sense amplification structure and memory architecture
US12033688B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2022 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Dec 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a sense amplification structure and a memory architecture. The sense amplification structure includes: a first PMOS transistor provided with a gate connected to a second readout bit line and a source connected to a first signal terminal; a first NMOS transistor provided with a gate connected to an initial bit line; a drain of the first PMOS transistor and a drain of the first NMOS transistor being connected to a first complementary readout bit line; a second PMOS transistor provided with a gate connected to the second complementary readout bit line; a second NMOS transistor provided with a gate connected to an initial complementary bit line and a source connected to a second signal terminal; a drain of the second PMOS transistor and a drain of the second NMOS transistor being connected to the first readout bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.