Protection of wire-bond ball grid array packaged integrated circuit chips
US12033925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2019 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Sep 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip includes a substrate having a first surface and a second surface opposite the first surface, and an integrated circuit mounted on a landing zone on the first surface of the substrate. The chip also includes contacts provided about the first surface in the peripheral region, and wire-bonds providing electrical connections between the integrated circuit and the contacts. The chip further includes solder ball connections provided in the peripheral region on the second surface, and connections provided in the substrate for connecting the electrical contacts on the first surface with the solder ball connections on the second surface. The substrate includes at least one conductive track routed through the landing zone region of the substrate, and the chip is configured such that an alteration in the at least one conductive track prevents operation of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.