Semiconductor layer structure with a thin blocking layer
US12034277B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 31, 2023 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | May 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S2301/173
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor layer structure may include a substrate, a blocking layer disposed over the substrate, and one or more epitaxial layers disposed over the blocking layer. The blocking layer may have a thickness of between 50 nanometers (nm) and 4000 nm. The blocking layer may be configured to suppress defects from the substrate propagating to the one or more epitaxial layers. The one or more epitaxial layers may include a quantum-well layer that includes a quantum-well intermixing region formed using a high temperature treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.