Processing device and method of updating translation lookaside buffer thereof
US12038850B1 · kind B1 · utility
1Cited by
0References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2023 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Nov 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neural processing device and a method of updating translation lookaside buffer thereof are provided. The neural processing device includes at least one processor module each of which includes at least one micro translation lookaside buffer (TLB), a hierarchical memory that is accessed by the at least one micro TLB, and a command processor configured to update the at least one micro TLB in a push mode by generating a first update signal which indicates update of the at least one micro TLB and transmitting the first update signal to the at least one micro TLB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.