Priority inversion mitigation techniques
US12039368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2021 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Nov 3, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.