Layout of semiconductor structure comprising column decoder
US12040021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Nov 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure include a layout of a semiconductor structure, including: a column decoder, wherein the column decoder includes a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region, and a NAND gate region. The first P-type transistor region is located above the first N-type transistor region, the second P-type transistor region is located above the first P-type transistor region, and the second N-type transistor region is located above the second P-type transistor region; the NAND gate region is adjacent to the first P-type transistor region, the second P-type transistor region, and the first N-type transistor region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.